1. Field of the Invention
The present invention relates generally to non-volatile memory technology and, more particularly, to a method of fabricating a floating gate of a non-volatile (e.g., flash) memory.
2. Description of the Related Art
In general, semiconductor memory devices may be classified into volatile memories that lose their contents (e.g., data) when power is turned off, and non-volatile memories that retain their contents (e.g., data) when power is turned off. Flash memory, a dominant type of non-volatile memory device, is widely used today for handheld devices, mobile and digital appliances, etc.
Flash memory stores data by trapping electrons from a semiconductor substrate in or on a floating gate when a voltage is applied to a control gate. Such a flash memory generally benefits from a high coupling ratio, which depends upon capacitance and/or the ability of the floating gate to store charge. In order to increase the capacitance of the floating gate, some approaches have been suggested in the art. One approach is to form an ONO (oxide-nitride-oxide) dielectric layer structure overlying, or as, the floating gate. Another approach is to form hemi-spherical grains on a surface of the floating gate. A third approach is to maximize the area of the floating gate.
Among them, the third approach may be unfavorable since it may limit any reduction in space between adjacent floating gates. The following is a description of a conventional technique for reducing space between adjacent floating gates.
FIG. 1 shows a layout of a floating gate of a conventional flash memory. FIG. 2 is a cross-sectional view taken along the line II-II of FIG. 1. Referring to FIGS. 1 and 2, a semiconductor substrate 100 has an active region 101 defined by a non-active isolation region 102. A plurality of floating gates 110 are formed at specific locations of the semiconductor substrate 100, being spaced apart from each other. As depicted in FIG. 2, a space (a) between the adjacent floating gates 110 restricts an increase in a width (b) of the floating gate.
FIGS. 3A to 3D show sequentially, in cross-sectional views, a conventional method of forming the floating gate.
Referring to FIG. 3A, a tunnel oxide layer 120, a polysilicon layer 130, and a silicon nitride layer 140 are formed in sequence on an upper surface of the semiconductor substrate 100 including the isolation region 102.
Referring to FIG. 3B, the silicon nitride layer 140 is selectively etched after performing a typical photolithographic process to pattern the silicon nitride layer 140.
FIG. 3C shows a step of forming the floating gate. In this step, the polysilicon layer (130 in FIG. 3B) is selectively etched using the patterned silicon nitride layer 140 as a hard mask. In result, the polysilicon layer 130 is patterned, exposing a surface of the isolation region 102, and therefore creating the floating gates 110.
FIG. 3D shows a step of forming a dielectric layer and a control gate. A dielectric layer such as an ONO layer 150 is formed on the floating gate 110. Then, a conductive material is deposited on the ONO layer 150 and patterned to form the control gate 160. Alternatively, polysilicon layer 130, dielectric layer 150 and a material for the control gate (not shown, but which may include, e.g., polysilicon) may be sequentially deposited, patterned and etched to form a structure such as that shown in FIG. 3D.
In the above-discussed conventional method, the floating gate 110 partly overlaps the isolation region 102 to reduce a space (indicated by a reference character “a” in FIG. 3C) between the adjacent floating gates 110. Furthermore, an overlap between the floating gate 110 and the isolation region 102 causes a sharp edge, as indicated by a reference character “A” in FIG. 3C, of the floating gate 110. Unfortunately, this shape of the floating gate 110 may deteriorate the reliability of the dielectric layer 150 overlying the floating gate 110. That is, the dielectric layer 150 may be under a lot of stress when a strong electric field is applied to the control gate 160 during operation of the flash memory. Therefore, the dielectric layer 150 may have a poor quality near edges, and further, this may have an adverse effect upon the state of electron storage and/or retention in the floating gate. Because of this, the flash memory may operate wrong.